Research Radar/Edge computing/China · United Kingdom · Singapore
Chip design claims 19 times the AI work per watt of an H100
A 28nm edge chip design for DeepSeek reports 109.4 TFLOPS per watt, which the authors put at 19.35 times an H100 at FP8. No chip was built, so the figures come from design tools.
A team from China, the United Kingdom and Singapore designed an edge processor block for DeepSeek inference called DSPE. Laid out in TSMC 28nm, it reports a peak energy efficiency of 109.4 TFLOPS per watt at 8 bit posit, which the paper says is 19.35 times an H100 GPU at FP8. The design was synthesised and placed and routed, but no chip was manufactured.
What happened
Ask a big AI model a hard question on your laptop and it answers. Then the fan spins up and the battery drops. This is because big models eat power. That is why most of them live in far away data centres.
A team wanted to move that work onto small devices, so they designed a chip block for it. They call it DSPE, which is short for DeepSeek Processing Element. It is built for one model family, DeepSeek.
The design leans on one simple idea. Much of the work a model does is work it has done before. This is because when a model reads a long text, each new word looks a lot like the last one. So the chip learns to spot near copies and skip them. It also makes each sum cheaper, and it stores each number in fewer bits.
The test
The paper is called “DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing”. It was written by Yuhan Zhang, Zhou Wang, Zhou Shu and colleagues. The team spans Northeastern University in Shenyang, Imperial College London, Imperial Global Singapore, Xidian University, the Chinese University of Hong Kong in Shenzhen, the Institute of Microelectronics of the Chinese Academy of Sciences and Nanyang Technological University. It appeared at the 63rd ACM and IEEE Design Automation Conference in July 2026.
The team wrote the chip in Verilog. Then they ran it through Synopsys tools to lay out a real 28nm design. The layout covers 8.23 square millimetres and holds four attention cores, and each core holds 64 small compute units.
One thing matters a lot here. No chip was made, so every power and speed figure comes from design software, not from a working part on a bench. The model workload was DeepSeek-V3 on a school-style test set called MMLU.
The result
The headline figure is 109.4 TFLOPS per watt, which is the peak energy score of the design at its 8 bit posit number format. The paper says that is 19.35 times the score of an H100 graphics card at FP8.
Read that as work done for each unit of power. A chip that scores twice as high does twice the sums on the same battery. Therefore this design claims to do about 19 times the AI work of a big data centre card, for each watt burned.
The parts add up like this. Skipping near copies cut reads from main memory by 33.5 percent and reads from on-chip memory by 36.2 percent. The cheaper multiplier cut the amount of calculation by 39.1 percent, and the tighter number format sped things up by 1.47 times.
Power draw runs from 122 to 345 milliwatts, which is phone territory. Top speed is 22.8 TFLOPS at 1.1 volts and 710 MHz. But watch the small print. The best energy score was taken at 0.6 volts and 200 MHz, which is the slowest, quietest setting, and not the fast one.
What it means
The thing that stops AI on your own device is not clever code. It is heat and battery. Therefore a model that needs 700 watts cannot live in your pocket. However, a block that needs a third of a watt can.
THE REAL LIMIT FOR AI ON SMALL DEVICES IS POWER, NOT SPEED. That is the line worth keeping.
There is a catch. This design is shaped around one model family. The tricks work because DeepSeek repeats itself in known ways. A chip tuned this tightly may age fast, because models change every few months, and that is a risk for any buyer.
Still, the direction is clear. Chip teams are chasing the repeated work inside models. If they win, small boxes will run answers that used to need a rack.
Business ideas from this paper
- A plain test report that measures watts used per answer on the small AI boxes people can actually buy. Who buys it: firms choosing hardware to run models in shops, clinics and farms. A price to test: 400 dollars for one board report. A one-week test: measure five popular boards, publish one chart free, and count how many firms ask for a board you have not tested yet.
- A small library that spots near copies in a stream of prompts and returns the saved answer instead of running the model again. Who buys it: app teams running models on their own servers or on device. A price to test: 20 dollars a month per app. A one-week test: release it free for one framework, then count installs and how many teams turn on the paid cache.
- A one week audit that finds repeated questions in a company’s chat logs and shows the money saved by caching them. Who buys it: support teams paying per token for a chat assistant. A price to test: 900 dollars per audit. A one-week test: offer a free scan of 1,000 logged prompts to ten firms, then count how many pay for the full audit.
How sure can you be?
Be careful with this one. The chip does not exist yet. The numbers come from design tools that estimate power and speed from a layout, and real silicon often falls short of those guesses.
The comparison is also uneven. The design is drawn in a 28nm process. However, an H100 is built in 4nm, and a newer process alone brings a large power gain. The paper compares its 8 bit posit score against the card’s FP8 score, and the two are not the same kind of number.
Then there is the missing figure. The design skips work it judges to be near enough, and that should cost some accuracy. The paper reports a 1.47 times speed gain from the number format at the same accuracy. It does not report an MMLU score for the model after the skipping, so you cannot see what the skipping cost.
Three things would settle it. A made chip, measured on a bench. An accuracy score before and after the skipping. A test on a model the design was not tuned for.
Do this today
If you run a model on your own hardware, measure watts per answer this week, and not only answers per second. That one number tells you whether the work can ever move off the data centre.
Source: DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing, DAC 2026, 63rd ACM/IEEE Design Automation Conference, July 2026. arXiv:2605.08615 · arxiv.org (peer reviewed).
Just Out Tech explains new research in plain language. This article was drafted with AI assistance and checked by a human against the original source.
- The DSPE design reports 109.4 TFLOPS per watt in TSMC 28nm, which the paper puts at 19.35 times the energy efficiency of an H100 GPU at FP8.
- Skipping near copies of work cut main memory reads by 33.5 percent and on-chip memory reads by 36.2 percent on DeepSeek-V3 with the MMLU test set.
- The peak energy figure was taken at the slowest setting of 0.6 volts and 200 MHz, while peak speed of 22.8 TFLOPS needs 1.1 volts and 710 MHz.
One group's design, implemented in Verilog and evaluated through synthesis and place-and-route on TSMC 28nm CMOS. The 109.4 TFLOPS/W figure comes from that flow. No fabricated or measured silicon is described.
- Who is building on it
- Co-author Xiaonan Tang is affiliated with Wisemaytech Co., Ltd., Beijing. The other authors are at universities and research institutes. The design targets inference for DeepSeek-V3 and is benchmarked against an NVIDIA H100. No code, RTL or model release is mentioned.
- Who paid for the research
- National Research Foundation, Prime Minister's Office, Singapore, under its IN-CYPHER Campus for Research Excellence and Technological Enterprise (CREATE) Programme.
Questions people ask
was this chip actually built?
No. The team wrote the design in Verilog, synthesised it with Synopsys Design Compiler and laid it out in 28nm with IC Compiler. The layout covers 8.23 square millimetres. Every power and speed number comes from those tools, not from a manufactured part.
what does TFLOPS per watt mean?
It is work done for each unit of power. A higher score means more sums on the same battery. The paper reports 109.4 TFLOPS per watt at peak for its 8 bit posit format, measured at 0.6 volts and 200 MHz.
how does the design save so much energy?
Three ways. It hashes vectors and skips ones that are near copies of earlier work. It picks a cheaper multiplication path when operands are similar. It folds repeated low bits out of the number format. Together these cut memory reads by about a third and calculation by 39.1 percent.
does the skipping hurt accuracy?
The paper does not say. It reports that the number format change keeps the same accuracy while running 1.47 times faster. It gives no MMLU accuracy score for the model after the pruning and approximate multiplication, so the cost of the skipping is not shown.
Mark Alex
Mark Alex is the founder and Managing Director of Real Biz Digital, a technology company operating out of Nairobi since 2018. He works in agentic AI and the Model Context Protocol, AI governance, enterprise software architecture and cybersecurity. He holds an MSc in Mechatronical Engineering from Obuda University in Budapest and a BSc in IT, Forensic Technology and Cybercrime, from USIU-Africa in Nairobi, and has published IEEE conference research on an AI-powered digital twin for greenhouse systems. He is the author of seven books. Between 2020 and 2024 he mentored more than 200 university students and interns in Nairobi. He writes every Just Out Tech article from the original research paper.